In today's computing environment, there is a growing demand for increased processing speed in order for the computer to operate efficiently. For instance, the resources of a modern computer can be saturated when the user specifies a finer mesh or higher resolution for the solution to a physical problem in areas such as hydrodynamics or 3-D graphics.
One way to increase processing speed is to utilize a large number of processors cooperatively. Processor cooperation is provided by the Scalable Coherent Interface ("SCI"), which is a high-speed packet transmission protocol that efficiently provides the functionality of bus-like transactions (read, write, lock, etc.) between processors. However, the initial physical implementations are based on Emitter-Coupled Logic ("ECL") signal levels, which consume more power than is practical in a low cost workstation environment. Additionally, ECL specifications require a 1 Gbyte per second bandwidth (for 16-bit data path), which is too expensive in a workstation environment.
In order to overcome the drawback of costly ECL signal levels, it has been proven to be cost effective to utilize a data path which is of sufficient bandwidth, but is narrower than the wider bandwidth of ECL signal levels. The combination of a high speed transmission environment and efficient protocols provides the link for multiple processors to cooperate in a low-cost workstation. Therefore, the IEEE Computer Society established the Low Voltage Differential Swing ("LVDS") standard, which is a signaling alternative to the ECL signal level protocol. The LVDS interface was standardized by the IEEE in the draft standard for Scalable Coherent Interface (SCI) LVDS, IEEE STANDARD, p. 1596.3, dated Sep. 9, 1993.
Essentially, an LVDS interface is a balanced I/O buffer driver that sends data by current signaling in a balanced interconnect environment. I/O buffer circuits are important in computers for maintaining high speed data transfer between packaged devices on a circuit board or between different backplanes. Typically, LVDS circuits operate in excess of 700 Mb/s in the 0.35.mu. CMOS technology, wherein a balanced pair of 50 .OMEGA. transmission lines are terminated across an on-chip resistance of 100 .OMEGA.. The output buffer must provide a signal current of 4 mA and be biased to cause a voltage drop across the on-chip input resistance from 1.4 to 1.0 volts. One drawback with conventional LVDS circuits is that the operating characteristics of the I/O circuits shift with variations in temperature and supply voltage. Further, even if different chips have identical supply voltages and are at the same temperature, the operating characteristics of buffers connected across different chips may vary due to variations introduced in fabrication.